1. Field of the Invention
The present invention relates generally to semiconductor manufacturing techniques and methods of forming electrical contacts in semiconductor substrates. More particularly, the present invention relates to methods of forming through-wafer interconnects in semiconductor substrates and structures resulting therefrom.
2. State of the Art
Semiconductor substrates often have vias extending therethrough, wherein the vias are filled with conductive materials to form interconnects (commonly known as a through-wafer interconnect, or “TWI”) used, for example, to connect circuitry on one surface of the semiconductor device to circuitry on another surface thereof, or to accommodate connection with external circuitry.
As used herein, a “via” refers to a hole or aperture having conductive material or a conductive member therein and which extends substantially through a substrate (e.g., from one surface substantially to another opposing surface). The via may be used accommodate electrical connection of a semiconductor device, an electrical component, or circuitry located on side of the substrate other than where bond pads have been formed. Vias are conventionally formed in a variety of substrates for a variety of uses. For example, interposers for single die packages, interconnects for multi-die packages, and contact probe cards for temporarily connecting semiconductor dice to a test apparatus often employ vias in their structures.
One known method of forming through-wafer interconnect structures includes a process known as spacer etching. Spacer etching is a relatively complicated and costly procedure. Referring to FIGS. 1A-1D a conventional method of forming a through-wafer interconnect using spacer etching is shown. FIG. 1A illustrates a semiconductor device 10 having a substrate 12 (such as a silicon substrate) with a layer of borophosphosilicate glass 14 (BPSG) disposed on a surface thereof. A bond pad 16 is formed over the layer of BPSG 14, and a passivation layer 18 overlies the bond pad 16. The passivation layer 18 is etched, such as by reactive ion (dry) etching, so as to define an opening in the passivation layer 18 at a location above the bond pad 16 as shown in FIG. 1B. Another etching process is used to form a hole or an aperture 20 that extends into the silicon substrate 12 portion of the semiconductor device 10 as shown in FIG. 1C.
As also depicted in FIG. 1C, a layer of insulative material 22 (e.g., a pulsed deposition layer or “PDL”) is deposited over the passivation layer 18, the bond pad 16, and an inner surface of the aperture 20. Optionally, a conductive liner may also be coated over the passivation layer 18, the bond pad 16, and an inner surface of the aperture 20. By forming the through-wafer interconnect in this manner, the layer of insulative material 22 is deposited on the exposed portion of bond pad 16 and must be subsequently removed. A spacer etching process may also be used to remove portions of the layer of insulative material 22, wherein portions of the layer of insulative material 22 are left on the inner surface of the aperture 20 and on the passivation layer 18 such as is illustrated in FIG. 1D. A conductive filler 24 is disposed in the aperture 20 and placed in contact with the bond pad 16. The filler 24 is exposed through the back surface of the substrate 12 to form the conductive via, as shown in FIG. 1D and as will be appreciated by those of ordinary skill in the art.
Under some conditions, e.g., the use of polyimide as a passivation layer, the PDL film will form cracks on the surface due to a mismatch in the coefficient of thermal expansion (“CTE”) of the materials. The subsequently performed spacer etch will replicate those cracks into the passivation layer ultimately causing shorting when metal is used to coat the sidewalls of the via.
It is a continuing desire to improve the manufacturing techniques and processes used in semiconductor fabrication including those associated with forming TWI structures. It would be advantageous to provide methods of forming through-wafer interconnect structures having improved efficiency and which are more cost effective than conventional techniques such as those which employ conventional spacer etching techniques.